KNDS, Elbit Systems Sign Teaming Agreement for EuroPULS at DSEI London

On the same subject

• 

  March 15, 2023 | International, Aerospace, C4ISR

  International industry partners announce collaboration agreement for GCAP advanced electronics

  The national industry champions for advanced defence electronics representing Japan, the UK and Italy have announced the signing of a collaboration agreement, the next formal step towards a permanent industrial...

• 

  November 25, 2019 | International, Aerospace

  Guerre électronique : Le ministère des Armées lance la réalisation du programme ARCHANGE

  PAR LAURENT LAGNEAU En février 2018, la ministre des Armées, Florence Parly, avait annoncé le lancement du programme « CUGE » pour « Capacité universelle de guerre électronique », destiné à remplacer les deux avions C-160 Gabriel actuellement en service au sein de l'Escadron électronique aéroporté 00.054 « Dunkerque ». Il était question d'équiper non pas deux mais trois avions avec cette nouvelle charge de guerre électronique. La seule indication donnée était qu'ils appartiendraient à la gamme « Falcon » de Dassault Aviation. Il fallut attendre le dernier salon de l'aéronautique et de l'espace du Bourget pour apprendre qu'il s'agirait de trois Falcon 8X, capables de franchir la distance de 6.450 nautiques [11.945 km] et de voler à la vitesse maximale de Mach 0,9 à l'altitude de 51.000 pieds [15.545 m]. Le tout en étant 30% plus « éco-efficient » que les autres appareils de mpeme catégorie. Restait alors à lancer le développement et l'acquisition de ces trois Falcon 8X adaptés à recevoir cette capacité universelle de guerre électronique. Ce qui vient d'être fait, à l'issue d'un comité ministériel d'investissement réuni le 18 novembre. « Le renseignement est indispensable à nos opérations militaires. Fruit de 10 ans d'études, le programme ARCHANGE équipera l'armée de l'air dès 2025. Sa mission : la guerre électronique, soit l'interception d'émissions radio et radar », a commenté Mme Parly, via Twitter. Pour rappel, ARCHANGE signifie « Avions de Renseignement à CHArge utile de Nouvelle GEnération. » « Résultat de dix années d'études sur des technologies de pointe, l'ensemble des capteurs constituant la charge utile sera développé par Thales. Cette charge utile, basée sur des technologies innovantes [antennes multi-polarisation, intelligence artificielle pour améliorer les traitements automatiques], permettra de détecter et d'analyser les signaux radar et de communication gr'ce à des capteurs intégrés sur un avion d'affaire Falcon 8X construit par Dassault Aviation », a expliqué le ministère des Armées. Outre la livraison des trois Falcon 8X « ARCHANGE », il est prévu de mettre en place une plateforme d'entraînement pour leurs futurs équipages sur la base aérienne d'Évreux. « Les systèmes ARCHANGE accroîtront significativement les capacités de renseignement électromagnétique aéroporté français et contribueront à l'effort particulier sur la fonction stratégique ‘connaissance et anticipation', gage de l'autonomie de décision de la France et de sa supériorité en opération », fait encore valoir le ministère des Armées. Mis en service il y a maintenant 30 ans, le remplacement des deux C-160 Gabriel est une priorité, d'autant plus que la flotte de Transall C-160 ne tardera pas à s'éteindre. Ces appareils sont essentiels pour le renseignement militaire français dans la mesure ils permettent de collecter et d'analyser des signaux électromagnétiques, et donc de pouvoir évaluer les forces d'un adversaire et d'adapter, par exemple, les contre-mesures électroniques à ses moyens de protection. http://www.opex360.com/2019/11/22/guerre-electronique-le-ministere-des-armees-lance-la-realisation-du-programme-archange/

• 

  March 29, 2019 | International, C4ISR, Security, Other Defence

  DARPA Seeks to Make Scalable On-Chip Security Pervasive

  For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25