28 mai 2020 | International, Aérospatial, Naval, Terrestre, C4ISR, Sécurité
WorldEdited by Divyanshu Dutta Roy (with inputs from PTI)Updated: May 28, 2020 08:01 am IST
Beijing:
Chinese President Xi Jinping on Tuesday ordered the military to scale up its battle preparedness, visualising the worst-case scenarios and asked them to resolutely defend the country's sovereignty. Though he did not mention any specific threat, his comments came amid a face-off between soldiers of India and China at the Line of Actual Control (LAC).
Xi, 66 who is also the General Secretary of the ruling Communist Party of China (CPC) and head of the two-million-strong military with prospects of lifelong tenure in power, made the remarks while attending a plenary meeting of the delegation of the People's Liberation Army (PLA) and People's Armed Police Force during the current parliament session being held in Beijing.
Xi ordered the military to think about worst-case scenarios, scale up training and battle preparedness, promptly and effectively deal with all sorts of complex situations and resolutely safeguard national sovereignty, security and development interests, state-run Xinhua news agency reported, without mentioning any specific issues that posed a threat to the country.
Several areas along the LAC in Ladakh and North Sikkim have witnessed major military build-up by both the Indian and Chinese armies recently, in a clear signal of escalating tension and hardening of respective positions by the two sides even two weeks after they were engaged in two separate face-offs. The nearly 3,500-km-long LAC is the de-facto border between the two countries.
China's military friction with the US has also been on the rise with the American navy stepping its patrols in the disputed South China Sea as well as the Taiwan Straits. Washington and Beijing are also engaged in a war of words over the origin of the coronavirus pandemic.
On May 22, China, the second-largest military spender after the US, hiked its defence budget by 6.6 per cent to $179 billion, nearly three times that of India, the lowest increment in recent years amidst the massive disruption caused to the communist giant's economy by the COVID-19 pandemic.
India has said the Chinese military was hindering normal patrolling by its troops along the LAC in Ladakh and Sikkim and strongly refuted Beijing's contention that the escalating tension between the two armies was triggered by trespassing of Indian forces across the Chinese side.
The Ministry of External Affairs said all Indian activities were carried out on its side of the border, asserting that India has always taken a very responsible approach towards border management. At the same time, it said, India was deeply committed to protect its sovereignty and security.
"Any suggestion that Indian troops had undertaken activity across the LAC in the Western sector or the Sikkim sector is not accurate. Indian troops are fully familiar with the alignment of the Line of Actual Control in the India-China border areas and abide by it scrupulously," MEA Spokesperson Anurag Srivastava said at an online media briefing last week.
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For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25