22 novembre 2023 | International, Terrestre, Sécurité
Project Nyx Alpha to boost UK Space Command’s domain awareness
A ground-based telescope in Crete will allow detection of satellites and other objects from LEO to GEO and Cislunar orbits.
14 mai 2020 | International, Aérospatial
No COVID impacts on Apache production, supply chain, says Boeing
By: Aaron Mehta
WASHINGTON — The COVID-19 pandemic has not had an impact on the production and delivery of Apache helicopters, but Boeing is closely watching the international supply chain for signs of slowdown, a company official said Tuesday.
The coronavirus impact going forward is difficult to predict, said T.J. Jamison, Boeing's director of vertical lift international sales. Still, he expressed a belief that the company should be able to stay on track with its plans to produce more than 100 Apache models in 2020.
While production on the CH-47 Chinook and V-22 Osprey in the Philadelphia, Pennsylvania, area was stopped for two weeks in April, the Mesa, Arizona, Boeing plant that produces the Apache never had to stop work. However, there have been a number of individuals working remotely, primarily from the sales team; it will likely be a month or more before they are all back working at their desks, Jamison said.
Some international customers have signaled that “we might need a potential slowdown in operations. But not one has said: ‘Hey, we need to cancel these orders because of the COVID-19 issue,' ” Jamison said. “There have been no cancellations, and there have been no significant requests for delay.”
However, just like the Pentagon, the company is closely watching the international supply chain. For the Apache, that includes fuselage production in Hydrabad, India (managed by Tata) and in Sacheon, South Korea (managed by Korea Aerospace Industries).
Boeing's decision to maintain two suppliers for that production has “served us very well” in the current situation, Jamison said, adding that while India has been hit hard by COVID-19 and is undergoing government-mandated shutdowns, the Korea Aerospace Industries plant is able to keep production on track.
“We really do not like to have a single point of failure with any of our components that we receive through the supply chain,” he said. “There hasn't been a dramatic impact to the supply chain today. Again, I don't have that crystal ball and I can't tell you how this pandemic is going to play out. But right now, there hasn't been a dramatic impact.”
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29 mars 2019 | International, Autre défense
DARPA: Designing Chips for Real Time Machine Learning
The current generation of machine learning (ML) systems would not have been possible without significant computing advances made over the past few decades. The development of the graphics-processing unit (GPU) was critical to the advancement of ML as it provided new levels of compute power needed for ML systems to process and train on large data sets. As the field of artificial intelligence looks towards advancing beyond today's ML capabilities, pushing into the realms of “learning” in real-time, new levels of computing are required. Highly specialized Application-Specific Integrated Circuits (ASICs) show promise in meeting the physical size, weight, and power (SWaP) requirements of advanced ML applications, such as autonomous systems and 5G. However, the high cost of design and implementation has made the development of ML-specific ASICs impractical for all but the highest volume applications. “A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain,” said Andreas Olofsson, a program manager in DARPA's Microsystems Technology Office (MTO). “Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. What's needed is the rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time.” DARPA's Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks. The goal of the RTML program is to create a compiler – or software platform – that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler's capabilities across two critical, high-bandwidth application areas: 5G networks and image processing. “Machine learning experts are proficient in developing algorithms but have little to no knowledge of chip design. Conversely, chip designers are not equipped with the expertise needed to inform the design of ML-specific ASICs. RTML seeks to merge these unique areas of expertise, making the process of designing ultra-specialized ASICs more efficient and cost-effective,” said Olofsson. Based on the application space's anticipated agility and efficiency, the RTML compiler provides an ideal platform for prototyping and testing fundamental ML research ideas that require novel chip designs. As such, DARPA plans to collaborate with the National Science Foundation (NSF) on this effort. NSF is pursuing its own Real Time Machine Learning program focused on developing novel ML paradigms and architectures that can support real-time inference and rapid learning. After the first phase of the DARPA RTML program, the agency plans to make its compiler available to NSF researchers to provide a platform for evaluating their proposed ML algorithms and architectures. During the second phase of the program, DARPA researchers will have an opportunity to evaluate the compiler's performance and capabilities using the results generated by NSF. The overall expectation of the DARPA-NSF partnership is to lay the foundation for next-generation co-design of RTML algorithms and hardware. “We are excited to work with DARPA to fund research teams to address the emerging challenges for real-time learning, prediction, and automated decision-making,” said Jim Kurose, NSF's head for Computer and Information Science and Engineering. “This collaboration is in alignment with the American AI Initiative and is critically important to maintaining American leadership in technology and innovation. It will contribute to advances for sustainable energy and water systems, healthcare logistics and delivery, and advanced manufacturing.” RTML is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. As a part of ERI Phase II, DARPA is supporting domestic manufacturing options and enabling the development of differentiated capabilities for diverse needs. RTML is helping to fulfill this mission by creating a means of expeditiously and cost-effectively generating novel chip designs to support emerging ML applications. Interested proposers will have an opportunity to learn more about the RTML program during a Proposers Day, which will be held at 675 North Randolph Street, Arlington, VA 22203 on Tuesday April 2, 2019 from 09:00 am – 03:00 pm EDT. Additional information about the event and registration are found here: https://www.fbo.gov/index?s=opportunity&mode=form&id=29e4d24ce31d2bf276a2162fae3d11cd&tab=core&_cview=0 Additional details on the RTML program are in the Broad Agency Announcement, published to fbo.gov: https://www.fbo.gov/index.php?s=opportunity&mode=form&id=a32e37cfad63edcba7cfd5d997422d93&tab=core&_cview=0 https://www.darpa.mil/news-events/2019-03-21
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8 août 2018 | International, C4ISR
Why small cyberattacks on power systems more likely than a long-running blackout
By: Justin Lynch Attacks on American power systems are likely to be small and localized, according to a cybersecurity firm, casting doubt on the ability of a foreign power to take down broad swaths of U.S. electric systems at once. Given current technology it is not reasonable to expect an enemy to shut down large portions of the U.S grid., but hackers do have the ability to target an individual location, Joe Slowik, an adversary hunter at the cybersecurity firm Dragos, told Fifth Domain at the Black Hat conference. “I might not be able to turn off the eastern seaboard, but if I want to cause a power blip in Washington D.C., that is feasible,” Slowik said. His cautions come after a series of warnings from the U.S. government regarding the potential for attacks on the power infrastructure. "Think about New England in January, the grid going down for three days. A lot of people are going to suffer and die,” Director of National Intelligence Dan Coats said during a July 13 event at the Hudson Institute. Full Article: https://www.fifthdomain.com/show-reporters/black-hat/2018/08/08/why-small-cyberattacks-on-power-systems-more-likely-than-a-long-running-blackout/