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  8 décembre 2020 | International, Terrestre

  DoD SBIR/STTR Component BAA Open: Army SBIR BAA 21.4, Topic A214-001

  The DoD Small Business and Technology Partnerships Office announces the opening of the following Broad Agency Announcement (BAA): Army SBIR 21.4 • A214-001: Identifying and Enabling Emerging Technology Leaders IMPORTANT DATES: • December 8, 2020: BAA opens, begin submitting proposals in DSIP • December 23, 2020: Topic Q&A (formerly SITIS) closes to new questions at 12:00 p.m. ET • January 12, 2021: BAA closes, full proposals must be submitted in DSIP no later than 12:00 p.m. ET The instructions and topics for these BAAs are available on DSIP at https://www.dodsbirsttr.mil/submissions/login and at https://rt.cto.mil/rtl-small-business-resources/sbir-sttr/. Please be sure to submit your proposals as early as possible in order to avoid unexpected delays due to high volume of traffic during the final hours before BAA close. Report system difficulties to the DSIP Help Desk IMMEDIATELY and include screenshots of any error messages received [NEW!] DSIP Registration and Login Effective August 13, 2020: The DoD SBIR/STTR Innovation Portal (DSIP) is now integrated with Login.gov – a government-wide registration platform that provides a seamless login experience. ALL Small Business Concerns (SBCs) are required to register for a Login.gov account and link it to your DSIP account. If you already have a Login.gov account, simply link your existing account to DSIP. To set up your Login.gov account, click the “Login/Register” button on the DSIP homepage, here: https://www.dodsbirsttr.mil/submissions/login. NOTE: The email address you use for Login.gov should match the email address associated with your existing DSIP account. If you do not recall the email address associated with your DSIP account, or if you already have an existing Login.gov account using a different email address, you will need your Firm's DUNS number and your Firm PIN in order to link your Login.gov account with your DSIP account. If the email address associated with your existing DSIP account has been used for multiple DSIP accounts within your Firm, you will also need your Firm's DUNS number and your Firm PIN in order to link your Login.gov account with your DSIP account. The Firm PIN can be obtained from your Firm Admin. You can view the Firm Admin's contact information by entering your Firm's DUNS number when prompted. If you are the Firm Admin, please ensure that you contact all DSIP users in your Firm and provide them with the Firm PIN. Job Aids and Help Videos are in the Learning & Support section of DSIP, here: https://www.dodsbirsttr.mil/submissions/learning-support/training-materials. ALL SBCs MUST complete your Login.gov setup as soon as possible to avoid delays in submitting proposals in DSIP. After setting up your Login.gov account, take a few minutes to log in and become familiar with DSIP. • Returning users can log in from the DSIP homepage. • For new program participants, follow the steps for New User Registration to create your account in DSIP. Topic Q&A (formerly SITIS) Proposers may submit technical questions through Topic Q&A page at https://www.dodsbirsttr.mil/submissions/login. All questions and answers are posted electronically for general viewing. Topic Q&A will close to new questions on December 23, 2020 at 12:00 p.m. ET, but will remain active to view questions and answers related to the topics until the BAA close. Proposers are advised to monitor Topic Q&A during the BAA period for questions and answers and frequently monitor DSIP for updates and amendments to the topics. Learning & Support Visit the Learning & Support section for Job Aids and Help Videos to guide you through submitting and viewing questions and answers in the Topic Q&A, preparing and submitting your proposal in DSIP, and more: https://www.dodsbirsttr.mil/submissions/learning-support/training-materials DSIP Help Desk Contact Info • Phone Number: 703-214-1333 • Email: DoDSBIRSupport@reisystems.com • Non-Holiday Hours: Monday – Friday, 9:00 a.m. – 5:00 p.m. ET • Please refer to the DSIP homepage for Help Desk availability on holidays. Thank you for your interest in the DoD SBIR/STTR Program. DoD SBIR/STTR Support Team To sign up and receive upcoming emails, please follow this link: https://secure.campaigner.com/CSB/Public/Form.aspx?fid=667492&ac=g9gk https://rt.cto.mil/rtl-small-business-resources/sbir-sttr/

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  29 mars 2019 | International, Autre défense

  DARPA: Designing Chips for Real Time Machine Learning

  The current generation of machine learning (ML) systems would not have been possible without significant computing advances made over the past few decades. The development of the graphics-processing unit (GPU) was critical to the advancement of ML as it provided new levels of compute power needed for ML systems to process and train on large data sets. As the field of artificial intelligence looks towards advancing beyond today's ML capabilities, pushing into the realms of “learning” in real-time, new levels of computing are required. Highly specialized Application-Specific Integrated Circuits (ASICs) show promise in meeting the physical size, weight, and power (SWaP) requirements of advanced ML applications, such as autonomous systems and 5G. However, the high cost of design and implementation has made the development of ML-specific ASICs impractical for all but the highest volume applications. “A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain,” said Andreas Olofsson, a program manager in DARPA's Microsystems Technology Office (MTO). “Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. What's needed is the rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time.” DARPA's Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks. The goal of the RTML program is to create a compiler – or software platform – that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler's capabilities across two critical, high-bandwidth application areas: 5G networks and image processing. “Machine learning experts are proficient in developing algorithms but have little to no knowledge of chip design. Conversely, chip designers are not equipped with the expertise needed to inform the design of ML-specific ASICs. RTML seeks to merge these unique areas of expertise, making the process of designing ultra-specialized ASICs more efficient and cost-effective,” said Olofsson. Based on the application space's anticipated agility and efficiency, the RTML compiler provides an ideal platform for prototyping and testing fundamental ML research ideas that require novel chip designs. As such, DARPA plans to collaborate with the National Science Foundation (NSF) on this effort. NSF is pursuing its own Real Time Machine Learning program focused on developing novel ML paradigms and architectures that can support real-time inference and rapid learning. After the first phase of the DARPA RTML program, the agency plans to make its compiler available to NSF researchers to provide a platform for evaluating their proposed ML algorithms and architectures. During the second phase of the program, DARPA researchers will have an opportunity to evaluate the compiler's performance and capabilities using the results generated by NSF. The overall expectation of the DARPA-NSF partnership is to lay the foundation for next-generation co-design of RTML algorithms and hardware. “We are excited to work with DARPA to fund research teams to address the emerging challenges for real-time learning, prediction, and automated decision-making,” said Jim Kurose, NSF's head for Computer and Information Science and Engineering. “This collaboration is in alignment with the American AI Initiative and is critically important to maintaining American leadership in technology and innovation. It will contribute to advances for sustainable energy and water systems, healthcare logistics and delivery, and advanced manufacturing.” RTML is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. As a part of ERI Phase II, DARPA is supporting domestic manufacturing options and enabling the development of differentiated capabilities for diverse needs. RTML is helping to fulfill this mission by creating a means of expeditiously and cost-effectively generating novel chip designs to support emerging ML applications. Interested proposers will have an opportunity to learn more about the RTML program during a Proposers Day, which will be held at 675 North Randolph Street, Arlington, VA 22203 on Tuesday April 2, 2019 from 09:00 am – 03:00 pm EDT. Additional information about the event and registration are found here: https://www.fbo.gov/index?s=opportunity&mode=form&id=29e4d24ce31d2bf276a2162fae3d11cd&tab=core&_cview=0 Additional details on the RTML program are in the Broad Agency Announcement, published to fbo.gov: https://www.fbo.gov/index.php?s=opportunity&mode=form&id=a32e37cfad63edcba7cfd5d997422d93&tab=core&_cview=0 https://www.darpa.mil/news-events/2019-03-21

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  21 juillet 2024 | International, Aérospatial

  Cybercriminals Exploit CrowdStrike Update Mishap to Distribute Remcos RAT Malware

  CrowdStrike warns of Remcos RAT malware targeting Latin America amid flawed update crisis causing IT disruptions.