3 décembre 2021 | International, Aérospatial

Lockheed unveils pared-down F-35 trainer with same software capability but a 90% reduced footprint

Lockheed Martin spent its own money developing this LITE trainer over the last 18 months after hearing signals from F-35 customers that they needed more training capacity for less cost.

https://www.defensenews.com/digital-show-dailies/itsec/2021/12/01/lockheed-unveils-pared-down-f-35-trainer-with-same-software-capability-but-a-90-reduced-footprint/

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  • The US submarine force should be silent no more

    23 août 2023 | International, Naval

    The US submarine force should be silent no more

    Instead of being the silent service, the U.S. undersea force will need to generate noise and hide in the resulting chaos.

  • Lockheed Martin-Built AEHF-5 Protected Communications Satellite Now in Transfer Orbit

    8 août 2019 | International, Aérospatial

    Lockheed Martin-Built AEHF-5 Protected Communications Satellite Now in Transfer Orbit

    The Lockheed Martin (NYSE:LMT)-built AEHF-5 satellite is now responding to the squadron's commands as planned. The squadron began "flying" the satellite shortly after it separated from its United Launch Alliance Atlas V 551 rocket approximately 5 hours and 40 minutes after the rocket's successful 6:13 a.m. ET liftoff. AEHF-5 complete a geostationary ring of five satellites delivering global coverage for survivable, highly secure and protected communications for strategic command and tactical warfighters operating on ground, sea and air platforms. Besides U.S. forces, AEHF also serves international partners including Canada, the Netherlands and the United Kingdom. "This fifth satellite adds an additional layer of flexibility for critical strategic and tactical protected communications serving the warfighter. This added resilience to the existing constellation will help ensure warfighters can connect globally to communicate and transmit data at all times," said Mike Cacheiro, vice president for Protected Communications at Lockheed Martin Space. "In the weeks ahead, AEHF-5 will move towards its operational orbit, deploy all of its solar arrays and antennas, and turn on its powerful communications payload for a rigorous testing phase prior to hand over to the Air Force." AEHF-5, with its advanced Extended Data Rate (XDR) waveform technology, adds to the constellation's high-bandwidth network. One AEHF satellite provides greater total capacity than the entire legacy five-satellite Milstar communications constellation. "Individual data rates increase five-fold compared to Milstar, permitting transmission of tactical military communications, such as real-time video, battlefield maps and targeting data," said Cacheiro. "AEHF affords national leaders anti-jam, always-on connectivity during all levels of conflict and enables both strategic and tactical users to communicate globally across a high-speed network that delivers protected communications in any environment." Lockheed Martin designed, processed and manufactured all five on-orbit AEHF satellites at its advanced satellite manufacturing facility in Sunnyvale, California. The next AEHF satellite, AEHF-6, is currently in full production in Silicon Valley and is expected to launch in 2020. The AEHF team includes the U.S. Air Force Military Satellite Communications Systems Directorate at the Space and Missile Systems Center, Los Angeles Air Force Base, Calif. Lockheed Martin Space, Sunnyvale, Calif., is the AEHF prime contractor, space and ground segments provider as well as system integrator, with Northrop Grumman Aerospace Systems, Redondo Beach, Calif., as the payload provider. For additional information, visit our website: http://www.lockheedmartin.com/aehf

  • DARPA Seeks to Make Scalable On-Chip Security Pervasive

    29 mars 2019 | International, C4ISR, Sécurité, Autre défense

    DARPA Seeks to Make Scalable On-Chip Security Pervasive

    For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25

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