June 25, 2020 | International, Aerospace
By: Valerie Insinna
WASHINGTON — The most widely used variant of the F-35 Joint Strike Fighter is currently unable to fly in thunderstorms after the discovery of damage to one of the systems it uses to protect itself from lightning, its prime contractor Lockheed Martin said Wednesday.
To safely fly in conditions where lightning is present, the F-35 relies on its Onboard Inert Gas Generation System, or OBIGGS, which pumps nitrogen-enriched air into the fuel tanks to inert them. Without this system, a jet could explode if struck by lightning.
However, damage to one of the tubes that distributes inert gas into the fuel tank was discovered during routine depot maintenance of an F-35A at Hill Air Force Base's Ogden Logistics Complex in Utah, Lockheed said in a statement.
Lockheed temporarily paused F-35 deliveries June 2-23 as the company validated whether it was properly installing OBIGGS systems. However, “it appears this anomaly is occurring in the field after aircraft delivery,” Lockheed said in a statement.
Lockheed has since delivered two F-35s, company spokesman Brett Ashworth said.
Because it cannot be confirmed that the OBIGGS system would function properly if the jet was hit by lightning, the F-35 Joint Program Office has opted to institute flight restrictions.
“As a safety precaution, the JPO recommended to unit commanders that they implement a lightning flight restriction for the F-35A, which restricts flying within 25 miles of lightning or thunderstorms,” Lockheed said. “We are working with the F-35 Joint Program Office (JPO) on a root cause corrective action investigation to determine next steps.”
The issue only seems to affect the F-35A conventional-takeoff-and-landing variant, which is used by the U.S. Air Force and the majority of international customers. The OBIGGS design is slightly different on the F-35B short-takeoff-and-vertical-landing variant due to the aircraft's lift fan, and the problem has not been observed on F-35C carrier-takeoff-and-landing aircraft, Ashworth said.
Bloomberg, which obtained a JPO memo dated June 5, reported that flawed tubes were found in 14 of the 24 “A” models inspected.
The JPO did not respond immediately to a request for comment.
For a plane nicknamed “Lightning II,” the F-35′s lightning protection systems have, ironically, become an embarrassing problem issue for the jet at times throughout its development.
The F-35 was prohibited from flying within 25 miles of lightning in the early 2010s after the Pentagon's weapons tester discovered deficiencies with the original OBIGGs system in getting enough inert gas into the fuel tanks. Those restrictions were rescinded after the OBIGGS was redesigned in 2014.
https://www.defensenews.com/air/2020/06/24/the-f-35-lightning-ii-cant-fly-in-lightning-once-again/
July 15, 2024 | International, Land, C4ISR, Security
Helsing announced that it will make a strategic move to expand to Estonia to supply Ai capabilities to Nato's eastern flank.
March 29, 2019 | International, C4ISR, Security, Other Defence
For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25
March 26, 2021 | International, Aerospace
Lockheed Martin and Northrop Grumman, instead of Boeing, were selected to compete to provide a new system aimed at knocking out long-range missiles fired by adversaries, estimated to cost $12 billion.