26 juin 2019 | International, Autre défense
By: Shawn Snow
No, it's not going to turn you into Marvel's Iron Man or Captain America, but you might run a better PFT or have fewer fitness-related injuries.
The Corps is on the hunt for new wearable gear with biosensing technology that can boost human performance and help build a more lethal battlefield force.
On Monday, the Corps posted a request for information to the government's business opportunities website to glean information from industry leaders on available tech to address the Corps' focus on human performance augmentation.
The Corps is looking at a number of possibilities from T-shirts, watches, wristbands or chest straps with embedded biosensing technology that can link to and download performance and physiological information to a database.
The new biosensing tech will afford battlefield commanders information about the “physiological status and readiness” of Marines, according to the RFI.
The new tech will also help commanders to "tailor conditioning and operational training in order to minimize injuries and optimize strength building and overall operational performance,” the posting reads.
But with any new tech — especially gear that can track, collect, store and upload data — comes with various operational security, or OPSEC, concerns.
In August 2018, the Defense Department banned the use of Fitbits and other fitness tracking devices for troops deployed overseas following data firm Strava's posting of a heat map that revealed the location and details of a number of U.S. bases and military outposts.
“The rapidly evolving market of devices, applications and services with geolocation capabilities presents a significant risk to the Department of Defense personnel on and off duty, and to our military operations globally,” then-Pentagon spokesman Army Col. Robert Manning III, said in a command release.
Manny Pacheco, a spokesman with Marine Corps Systems Command, told Marine Corps Times that there are “OPSEC concerns with any effort” to procure new gear for Marines and that the Corps will look for “ways to mitigate those concerns.”
“In this particular case we are just looking at technologies for potential future use and will address the OPSEC issues as they arise,” Pacheco said about the RFI for the new wearable tech.
The Corps listed human performance augmentation as a key focus area headed into 2020.
24 novembre 2021 | International, C4ISR
The authors want the White House to craft a North Star vision to coordinate civil, commercial and national security space efforts.
29 mars 2019 | International, Autre défense
The current generation of machine learning (ML) systems would not have been possible without significant computing advances made over the past few decades. The development of the graphics-processing unit (GPU) was critical to the advancement of ML as it provided new levels of compute power needed for ML systems to process and train on large data sets. As the field of artificial intelligence looks towards advancing beyond today's ML capabilities, pushing into the realms of “learning” in real-time, new levels of computing are required. Highly specialized Application-Specific Integrated Circuits (ASICs) show promise in meeting the physical size, weight, and power (SWaP) requirements of advanced ML applications, such as autonomous systems and 5G. However, the high cost of design and implementation has made the development of ML-specific ASICs impractical for all but the highest volume applications. “A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain,” said Andreas Olofsson, a program manager in DARPA's Microsystems Technology Office (MTO). “Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. What's needed is the rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time.” DARPA's Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks. The goal of the RTML program is to create a compiler – or software platform – that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler's capabilities across two critical, high-bandwidth application areas: 5G networks and image processing. “Machine learning experts are proficient in developing algorithms but have little to no knowledge of chip design. Conversely, chip designers are not equipped with the expertise needed to inform the design of ML-specific ASICs. RTML seeks to merge these unique areas of expertise, making the process of designing ultra-specialized ASICs more efficient and cost-effective,” said Olofsson. Based on the application space's anticipated agility and efficiency, the RTML compiler provides an ideal platform for prototyping and testing fundamental ML research ideas that require novel chip designs. As such, DARPA plans to collaborate with the National Science Foundation (NSF) on this effort. NSF is pursuing its own Real Time Machine Learning program focused on developing novel ML paradigms and architectures that can support real-time inference and rapid learning. After the first phase of the DARPA RTML program, the agency plans to make its compiler available to NSF researchers to provide a platform for evaluating their proposed ML algorithms and architectures. During the second phase of the program, DARPA researchers will have an opportunity to evaluate the compiler's performance and capabilities using the results generated by NSF. The overall expectation of the DARPA-NSF partnership is to lay the foundation for next-generation co-design of RTML algorithms and hardware. “We are excited to work with DARPA to fund research teams to address the emerging challenges for real-time learning, prediction, and automated decision-making,” said Jim Kurose, NSF's head for Computer and Information Science and Engineering. “This collaboration is in alignment with the American AI Initiative and is critically important to maintaining American leadership in technology and innovation. It will contribute to advances for sustainable energy and water systems, healthcare logistics and delivery, and advanced manufacturing.” RTML is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. As a part of ERI Phase II, DARPA is supporting domestic manufacturing options and enabling the development of differentiated capabilities for diverse needs. RTML is helping to fulfill this mission by creating a means of expeditiously and cost-effectively generating novel chip designs to support emerging ML applications. Interested proposers will have an opportunity to learn more about the RTML program during a Proposers Day, which will be held at 675 North Randolph Street, Arlington, VA 22203 on Tuesday April 2, 2019 from 09:00 am – 03:00 pm EDT. Additional information about the event and registration are found here: https://www.fbo.gov/index?s=opportunity&mode=form&id=29e4d24ce31d2bf276a2162fae3d11cd&tab=core&_cview=0 Additional details on the RTML program are in the Broad Agency Announcement, published to fbo.gov: https://www.fbo.gov/index.php?s=opportunity&mode=form&id=a32e37cfad63edcba7cfd5d997422d93&tab=core&_cview=0 https://www.darpa.mil/news-events/2019-03-21
7 mars 2023 | International, C4ISR
Northrop Grumman connected previously incompatible links and networks using an Open Mission Systems compliant radio, Resilient Network Controller, machine learning algorithms and gateway technology