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  16 juillet 2018 | International, Terrestre

  The Army’s next machine gun could fire caseless ammo — and one of these companies might build it

  By: Todd South The replacement for the Army's 5.56mm Squad Automatic Weapon could be an entirely new type of light machine gun that fires not only a different caliber round, but caseless ammunition. That's because one of the five companies recently awarded contracts to produce a weapon prototype by this time next year has been building weapons to fire that type of ammo for the past 14 years. A notice posted Thursday included the identities of the five companies: AAI Corporation Textron Systems in Hunt Valley, Maryland. FN America LLC.in Columbia, South Carolina. General Dynamics-OTS Inc. PCP Tactical, LLC. in Vero Beach, Florida. Sig Sauer Inc. in Newington, New Hampshire. The companies were awarded a contract to provide a prototype for the Army's Next Generation Squad Automatic Rifle, or NGSAR. The light machine gun is the first planned major overhaul of small arms in decades. Based on the notice, it appears that FN America has been granted an award to provide two prototypes, while the other four companies will provide a single prototype. Those prototypes will help the Army decide what's possible given their extensive requirements for the new weapon. There will then be an open competition following those submissions, where more companies can try to get in on the weapon that will utlimately replace the M249 SAW and influence the M4 replacement, as well. It is also the first weapon of its type that could mean a dramatic shift in all small arms, with follow-on changes planned for an individual carbine that will likely incorporate the machine gun changes, officials have said. Current efforts include work on a lighter machine gun that fires a government-designed 6.8mm round, which falls between the lighter 5.56mm and heavier 7.62mm used in heavy machine guns. But submissions can include other calibers, so long as they meet accuracy and lethality requirements for the new weapon, officials have said. In the Textron release, the company says the prototype will be based on their cased-telescoped weapons and ammunition portfolio. The company has designed both a carbine and light machine gun variant, which have been displayed publicly in recent years. The NGSAR will be an “intermediate caliber, high-velocity, magazine-fed system,” according to the release. It will weigh less than 12 pounds with ammunition that weighs 20 percent less than the traditional brass case ammo. The weapon will be at most 35 inches long and be able to fire 60 rounds per minute for 15 minutes without a barrel change. Accuracy matters too. A shooter must be able to hit standard targets at 50 meters while standing, with three- to five-round bursts at least 70 percent of the time. The companies also received awards for advanced weapons and fire control technologies, for the Next Generation Squad Weapons Technologies, the umbrella program for advancing small arms, and for the fire control capability. Wayne Prender, vice president of Applied Technologies & Advanced Programs at Textron Systems, told Army Times Thursday that he couldn't discuss details of their fire control submissions configuration. But he did talk about some of the capabilites they plan to provide. “We're offering up a solution set, day/night system optics with a laser range finder, integrated ballistic computer for computation of the target,” Prender said. Last year Textron unveiled a 6.5mm carbine using their ammunition. The NSGW program aims to use an intermediate caliber, likely in the 6mm range, such as their 6.8mm ammunition development. But Prender said he couldn't discuss details of the caliber submission for the weapon prototype. Army leaders have said that advancements will come in stages and initial fire controls will be a part of the first fielded system, but that improved fire controls with additional upgrades will be incorporated into the system. https://www.armytimes.com/news/your-army/2018/07/12/the-armys-next-machine-gun-could-fire-caseless-ammo-and-one-of-these-companies-might-build-it/

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  1 avril 2020 | International, Aérospatial

  Raytheon, Missile Defense Agency sign landmark $2 billion Standard Missile-3 contract

  Tucson, Ariz., March 30, 2020 /PRNewswire/ -- Raytheon Company (NYSE: RTN) will produce and deliver SM-3(®) Block IB interceptors under a $2.1 billion, multi-year U.S. Missile Defense Agency contract. It is the first multi-year contract for the SM-3 program, and covers fiscal years 2019-2023. SM-3 is the only ballistic missile interceptor that can be launched on land and at sea. It is deployed worldwide and has achieved more than 30 exoatmospheric intercepts against ballistic missile targets. "This procurement deal is a win-win for government and industry," said Dr. Mitch Stevison, Raytheon Strategic and Naval Systems vice president. "Efficiencies gained from this contract will allow us to reduce costs, continue to improve the SM-3 and deliver an important capability to our military." The Block IB variant achieved full-rate production in 2017. The company has delivered more than 400 SM-3 rounds over the lifetime of the program. About Raytheon Raytheon Company, with 2019 sales of $29 billion and 70,000 employees, is a technology and innovation leader specializing in defense, civil government and cybersecurity solutions. With a history of innovation spanning 98 years, Raytheon provides state-of-the-art electronics, mission systems integration, C5I(®) products and services, sensing, effects, and mission support for customers in more than 80 countries. Raytheon is headquartered in Waltham, Massachusetts. Follow us on Twitter. Media Contact Doug Shores +1.256.527.5196 rmspr@raytheon.com View original content to download multimedia:http://www.prnewswire.com/news-releases/raytheon-missile-defense-agency-sign-landmark-2-billion-standard-missile-3-contract-301031740.html SOURCE Raytheon Company

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  29 mars 2019 | International, C4ISR, Sécurité, Autre défense

  DARPA Seeks to Make Scalable On-Chip Security Pervasive

  For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25