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  15 juin 2021 | International, Aérospatial, Naval, Terrestre, C4ISR, Sécurité

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  29 mars 2019 | International, C4ISR, Sécurité, Autre défense

  DARPA Seeks to Make Scalable On-Chip Security Pervasive

  For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25

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  9 novembre 2020 | International, Aérospatial

  Competitors protest awards to SpaceX and L3Harris for hyperonic weapon tracking satellites

  Nathan Strout WASHINGTON - Raytheon and Airbus are protesting two recent awards for eight missile tracking satellites issued to SpaceX and L3Harris, putting into question the Space Development Agency's tight schedule to get its initial constellation on orbit in 2022. The news was first reported by Aviation Week. Under the Oct. 5 award in question, SpaceX and L3Harris were issued contracts to design and develop four satellites equipped with wide field of view (WFOV) overhead persistent infrared (OPIR) sensors. The eight satellites would form tranche 0 of SDA's tracking layer, which the military is building to track hypersonic weapons from space. L3Harris received $193 million, while SpaceX received $149 million. Airbus U.S. Space & Defense first filed its protest of the award Oct. 28, while Raytheon filed its own protest on Nov. 3. A stop work order has been issued for SpaceX and L3Harris. “SDA is working with the GAO to achieve fast, accurate and equitable resolution to the protests received from Airbus and Raytheon on the agency's Tracking Tranche 0 contracts," an SDA spokesperson said in a statement. “SDA is committed to full and open competition whenever practicable and the agency understands protests are a potential and not uncommon part of that process.” The tracking layer is one of several capabilities being built into the agency's planned mega-constellation known as the National Defense Space Architecture. SDA is using a spiral development approach to build out that constellation, by adding more satellites every two years. The first tranche, which would include the eight missile tracking satellites in question, will include about 30 satellites set to launch in 2022. By the end of 2026, the agency wants to have hundreds of satellites in orbit. While Raytheon declined to comment, Airbus U.S. Space & Defense told C4ISRNET in a statement that concerns over the government's evaluation process for the proposals led the company to protest the award. “While determined highly competitive, Airbus U.S. Space & Defense, Inc. was ultimately not selected by SDA for award. Our post-award debrief review identified concerns about the government's evaluation process, and as a result, we have filed a protest with the U.S. Government Accountability Office (GAO),” an Airbus U.S. spokesperson said in a statement. “Airbus U.S. believes its proposal based on the ARROW commodity satellite bus and the Airbus OneWeb Satellites' operational manufacturing facility in Florida fits SDA's evaluation criteria for commercial commoditized buses manufactured at scale.” At the time of the awards, SDA Director Derek Tournear told C4ISRNET the awards were the result of a full and open competition, with the selection based purely on technical merit. Tournear praised both SpaceX and L3Harris in that interview, emphasizing both companies' plans to meet the agency's aggressive schedule. “SpaceX had a very credible story along that line — a very compelling proposal. It was outstanding,” he said. “They are one of the ones that have been at the forefront of this commercialization and commodification route.” In addition, “L3Harris had an extremely capable solution. They have a lot of experience flying affordable, rapid, small satellite buses for the department,” he said. “They had the plant and the line in place in order to produce these to hit our schedule.” https://www.c4isrnet.com/battlefield-tech/space/2020/11/06/competitors-protest-awards-to-spacex-and-l3harris-for-hyperonic-weapon-tracking-satellites/