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  December 4, 2020 | International, Aerospace

  Textron Systems awarded contract to build 36 new SHADOW® aircraft for the U.S Army

  Hunt Valley, MD. December 2, 2020– Textron Systems Corporation, a Textron Inc. (NYSE: TXT) company, announced today the sale of 36 Shadow aircraft in the latest Block III configuration to the U.S. Army. The total contract award value of $66 million includes ongoing engineering services to continue fielding and supporting the new Block III system configuration. “We are proud to maintain our strong partnership of more than 20 years with the U.S. Army on the Shadow program,” said Senior Vice President David Phillips of Textron Systems. “The Shadow Block III will support the customer with the enhanced capabilities soldiers need to fulfill today's and tomorrow's missions.” The Shadow Block III system builds on the proven success of previous configurations. The upgraded system incorporates design improvements, allowing for increased availability to operate in adverse weather conditions, the latest high-definition day-and-night video payload, increased engine power and reliability with a reduced acoustic signature, enhanced manned-unmanned teaming with the Army's Apache assets and an advanced communications relay. The Shadow Block III system is ready and able to provide aerial support to our customers, even in the most challenging of environments. With 1.2 million flight hours and counting, the Shadow system's proven track record provides a solid foundation for continued development and use around the world. About Textron Systems Textron Systems is a world leader in unmanned air, surface and land products, services and support for aerospace and defense customers. Harnessing agility and a broad base of expertise, Textron Systems' innovative businesses design, manufacture, field and support comprehensive solutions that expand customer capabilities and deliver value. For more information, visit www.textronsystems.com About Textron Inc. Textron Inc. is a multi-industry company that leverages its global network of aircraft, defense, industrial and finance businesses to provide customers with innovative solutions and services. Textron is known around the world for its powerful brands such as Bell, Cessna, Beechcraft, Hawker, Jacobsen, Kautex, Lycoming, E-Z-GO, Arctic Cat, Textron Systems, and TRU Simulation + Training. For more information, visit www.textron.com. Certain statements in this press release are forward-looking statements which may project revenues or describe strategies, goals, outlook or other non-historical matters; these statements speak only as of the date on which they are made, and we undertake no obligation to update or revise any forward-looking statements. These statements are subject to known and unknown risks, uncertainties, and other factors that may cause our actual results to differ materially from those expressed or implied by such forward-looking statements, including, but not limited to, risks related to U.S. Government contracts as described in our filings with the Securities and Exchange Commission. MEDIA CONTACT Textron Systems Public Relations Team 978-657-2020 publicrelations@textronsystems.com View source version on Textron Systems: https://investor.textron.com/news/news-releases/press-release-details/2020/TEXTRON-SYSTEMS-AWARDED-CONTRACT-TO-BUILD-36-NEW-SHADOW-AIRCRAFT-FOR-THE-U.S.-ARMY/default.aspx

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  June 23, 2024 | International, Land

  Patriot in focus amid missile defense system shortage

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  March 29, 2019 | International, Other Defence

  DARPA: Designing Chips for Real Time Machine Learning

  The current generation of machine learning (ML) systems would not have been possible without significant computing advances made over the past few decades. The development of the graphics-processing unit (GPU) was critical to the advancement of ML as it provided new levels of compute power needed for ML systems to process and train on large data sets. As the field of artificial intelligence looks towards advancing beyond today's ML capabilities, pushing into the realms of “learning” in real-time, new levels of computing are required. Highly specialized Application-Specific Integrated Circuits (ASICs) show promise in meeting the physical size, weight, and power (SWaP) requirements of advanced ML applications, such as autonomous systems and 5G. However, the high cost of design and implementation has made the development of ML-specific ASICs impractical for all but the highest volume applications. “A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain,” said Andreas Olofsson, a program manager in DARPA's Microsystems Technology Office (MTO). “Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. What's needed is the rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time.” DARPA's Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks. The goal of the RTML program is to create a compiler – or software platform – that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler's capabilities across two critical, high-bandwidth application areas: 5G networks and image processing. “Machine learning experts are proficient in developing algorithms but have little to no knowledge of chip design. Conversely, chip designers are not equipped with the expertise needed to inform the design of ML-specific ASICs. RTML seeks to merge these unique areas of expertise, making the process of designing ultra-specialized ASICs more efficient and cost-effective,” said Olofsson. Based on the application space's anticipated agility and efficiency, the RTML compiler provides an ideal platform for prototyping and testing fundamental ML research ideas that require novel chip designs. As such, DARPA plans to collaborate with the National Science Foundation (NSF) on this effort. NSF is pursuing its own Real Time Machine Learning program focused on developing novel ML paradigms and architectures that can support real-time inference and rapid learning. After the first phase of the DARPA RTML program, the agency plans to make its compiler available to NSF researchers to provide a platform for evaluating their proposed ML algorithms and architectures. During the second phase of the program, DARPA researchers will have an opportunity to evaluate the compiler's performance and capabilities using the results generated by NSF. The overall expectation of the DARPA-NSF partnership is to lay the foundation for next-generation co-design of RTML algorithms and hardware. “We are excited to work with DARPA to fund research teams to address the emerging challenges for real-time learning, prediction, and automated decision-making,” said Jim Kurose, NSF's head for Computer and Information Science and Engineering. “This collaboration is in alignment with the American AI Initiative and is critically important to maintaining American leadership in technology and innovation. It will contribute to advances for sustainable energy and water systems, healthcare logistics and delivery, and advanced manufacturing.” RTML is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. As a part of ERI Phase II, DARPA is supporting domestic manufacturing options and enabling the development of differentiated capabilities for diverse needs. RTML is helping to fulfill this mission by creating a means of expeditiously and cost-effectively generating novel chip designs to support emerging ML applications. Interested proposers will have an opportunity to learn more about the RTML program during a Proposers Day, which will be held at 675 North Randolph Street, Arlington, VA 22203 on Tuesday April 2, 2019 from 09:00 am – 03:00 pm EDT. Additional information about the event and registration are found here: https://www.fbo.gov/index?s=opportunity&mode=form&id=29e4d24ce31d2bf276a2162fae3d11cd&tab=core&_cview=0 Additional details on the RTML program are in the Broad Agency Announcement, published to fbo.gov: https://www.fbo.gov/index.php?s=opportunity&mode=form&id=a32e37cfad63edcba7cfd5d997422d93&tab=core&_cview=0 https://www.darpa.mil/news-events/2019-03-21