Better Stryker Tech and new polar icebreakers | Defense Dollars

On the same subject

• 

  October 26, 2022 | International, Aerospace

  Dans la lutte anti-drones, Thalès a développé PARADE pour les neutraliser

  A Brétigny-sur-Orge, les entreprises Thales et CS Group se sont associées pour créer le système PARADE, et lutter contre la menace émergente des drones

• 

  March 29, 2019 | International, C4ISR, Security, Other Defence

  DARPA Seeks to Make Scalable On-Chip Security Pervasive

  For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25

• 

  September 28, 2018 | International, Naval

  LOCKHEED MARTIN AND FINCANTIERI MARINETTE MARINE AWARDED CONTRACT TO BUILD LITTORAL COMBAT SHIP 29

  Construction will begin in first half of 2019 WASHINGTON, Sept. 27, 2018 – The U.S. Navy awarded the Lockheed Martin (NYSE: LMT) and Fincantieri Marinette Marine (FMM) team a fixed price incentive fee contract to build an additional Littoral Combat Ship (LCS). LCS 29 will be built in Marinette, Wisconsin, at FMM, the Midwest's only naval shipyard, and is the 15th Freedom-variant LCS ordered by the U.S. Navy to date. The team will leverage capital investment and improvement in the shipyard and efficiencies created with serial production to maintain high quality at an affordable cost. "We are excited to continue our partnership with the U.S. Navy and FMM to build and deliver increasingly capable ships to the fleet,” said Joe DePietro, vice president, Lockheed Martin Small Combatants and Ship Systems. "With the Freedom-variant in serial production, we continue to enhance efficiency, incorporate capability while maintaining ship and program affordability." Since the LCS program's inception, Freedom-variant LCS production has injected hundreds of millions of dollars into local economies throughout the Midwest. The program supports thousands of direct and indirect jobs throughout the United States, including more than 7,500 in Michigan and Wisconsin alone. The Lockheed Martin and FMM team is in full-rate production of the Freedom-variant, and has delivered seven ships to the U.S. Navy to date, including two this year – the future USS Sioux City and the future USS Wichita. There are seven ships in various stages of construction at Fincantieri Marinette Marine. Lockheed Martin's Freedom-variant LCS is highly maneuverable, lethal and adaptable. Originally designed to support focused missions such as mine warfare, anti-submarine warfare and surface warfare, the team continues to evolve capabilities based on rigorous Navy operational testing; sailor feedback and multiple successful fleet deployments. The Freedom-variant LCS integrates new technology and capability to affordably support current and future mission capability from deep water to the littorals. For additional information, visit: www.lockheedmartin.com/lcs. About Lockheed Martin Headquartered in Bethesda, Maryland, Lockheed Martin is a global security and aerospace company that employs approximately 100,000 people worldwide and is principally engaged in the research, design, development, manufacture, integration and sustainment of advanced technology systems, products and services. This year the company received three Edison Awards for ground-breaking innovations in autonomy, satellite technology and directed energy. About Fincantieri Marinette Marine Fincantieri is the leading western shipbuilder with a rich history dating back more than 230 years, and a track record of building more than 7,000 ships. Fincantieri Marine Group is the American subsidiary of Fincantieri, and operates three Great Lakes Shipyards: Fincantieri Marinette Marine, Fincantieri Bay Shipbuilding, and Fincantieri ACE Marine. Fincantieri Marine Group's more than 2,100 steelworkers, craftsman, engineers and technicians in the United States specialize in the design, construction and maintenance of merchant ships and government vessels, including for the United States Navy and Coast Guard. About Gibbs & Cox Gibbs & Cox, the nation's leading independent maritime solutions firm specializing in naval architecture, marine engineering and design, is headquartered in Arlington, Virginia. The company, founded in 1929, has provided designs for nearly 80 percent of the current U.S. Navy surface combatant fleet; approaching 7,000 naval and commercial ships have been built to Gibbs & Cox designs. https://news.lockheedmartin.com/2018-09-27-Lockheed-Martin-and-Fincantieri-Marinette-Marine-Awarded-Contract-to-Build-LCS-29