U.S. Army Awards Boeing $160 Million to Continue Chinook Rotor Blade Support

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  21 juillet 2022 | International, Aérospatial, Naval, Terrestre, C4ISR, Sécurité, Autre défense

  For emerging tech, DoD funds $100M in new projects to help bridge ‘valley of death’

  “APFIT holds great promise to transform the way the Department procures next generations solutions,” Heidi Shyu, undersecretary of defense for research and engineering, said. “This pilot program is well positioned to be a key asset as we continue to work to bridge the valley of death."

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  1 avril 2020 | International, Aérospatial

  Saab delivers virtual Gripen E program update

  by Chris Thatcher The Saab Gripen E test program has surpassed 300 flight hours and the company is preparing to deliver production aircraft to the Swedish Air Force in 2020. “We are proceeding according to plan and are delivering according to our customers' expectations,” Eddy de la Motte, the head of Saab's Gripen E/F business unit, told webinar viewers during a briefing on Mar. 26. The annual update on the Gripen program was moved to an online forum in response to the coronavirus pandemic. Although Sweden has for now adopted a notably different approach to addressing the spread of COVID-19 than its neighbours – most businesses remain open – defence and aerospace journalists and other interested attendees were confined to virtual participation. “Saab is not one of those companies that is feeling immediate consequences because of the situation given a large order backlog and the business model that we use,” said Ellen Molin, head of Business Area Support Services. “We are doing everything we can to work on development and production.” The Gripen E is among three fighter jets contending to replace the Royal Canadian Air Force fleet of CF-188 Hornets. The others are the Lockheed Martin F-35A Lightning II and the Block III Boeing FA-18E/F Super Hornet. The Gripen E is the only one not yet in service. The briefing was an opportunity for Saab to highlight the progress of the flight test program and forthcoming deliveries to the first customers, Sweden and Brazil. The test program now includes six aircraft and will be expanding to two sites this year involving test pilots from Saab, the Swedish defence materiel administration, and the Swedish Air Force. The accelerated test and verification program will be “more efficient,” said de la Motte. “We are now shifting focus to more testing on the tactical systems and the sensors.” Saab had high expectations for the Gripen E's enhanced fused sensor suite and decision-support capabilities before flight testing began, he said. But the Active Electronically-Scanned Array (AESA) radar, passive infrared search and track (IRST) sensor, tailored datalink and multi-function electronic warfare (EW) system “are preforming better than expected.” Testing has also included an electronic jammer pod to complement the internal active EW system, flights with the MBDA Meteor beyond-visual-range air-to-air missile, and firing of the short-range IRIS-T air-to-air missile. The first production aircraft rolled off the line in Linköping, Sweden earlier this year, and the second and third will be delivered to Sweden later in 2020. Among other milestones, Saab turned over the first test aircraft to the Brazilian Air Force in August 2019. Its arrival in Brazil is scheduled for the end of 2020. Brazil has ordered 36 jets, 28 in the single-seat E variant and eight in the two-seat F model. In advance of the Brazilian flight test program and the launch of a Gripen flight test centre in Brazil, Saab has transferred aircraft intellectual property and knowledge to hundreds of Brazilian technicians, test engineers and pilots at its production facility in Linköping. Furthermore, the Gripen Design and Development Centre in Brazil has cut the first metal on the F-model two seat variant, to be delivered in 2023. Saab is also hoping to expand its customer base as the Gripen E enters service. In February, the company demonstrated two of its test aircraft at Pirkkala Air Base in southern Finland as part of the HX Challenge, the first stage of a capability assessment of five aircraft vying to replace the Finnish Air Force fleet of F/A-18 C and D Hornets. The Gripen is up against the Eurofighter Typhoon, Dassault Rafale, Lockheed Martin F-35A and Boeing F/A-18 Super Hornet. The two aircraft were demonstrated alongside a Saab GlobalEye airborne early warning and control platform, a multi-role air, maritime and ground surveillance system based on the Bombardier Global 6000/6500 jet. As part of a package with Finland, Saab is proposing to transfer intellectual property to operate maintenance, repair and overhaul facilities, spares production, final assembly and a development and sustainment centre. “We fully understand the needs of national security and the ability to control critical technology,” said de la Motte. A similar offer is likely to be part of Saab's pitch to Canada when the request for proposals closes on June 30. In March, the company announced a “Gripen for Canada Team” that includes IMP Aerospace & Defence, CAE, Peraton Canada and GE Aviation. De la Motte said the proposal for 88 Gripen E jets would include “high skilled jobs” as well as aircraft and systems built by Canadians. Both de la Motte and Molin emphasized the “smart and cost-efficient support concept inherent in the aircraft design” that now includes the ability to 3D print spare parts for battle damage repair in a forward hangar to allow grounded aircraft to return to a main operating base. That efficiency was underscored by Col Torgny Fälthammar, head of the Gripen program for the Air Staff of the Swedish Air Force (SAF). A former Saab 37 Viggen and Gripen C fighter pilot, he noted the SAF “operates in a domain where the time to react is sometimes very short – the aircraft and systems we face have a very high velocity.” Since Sweden can't field superior numbers, “we have to strive for the best balance between technology, competence and tactics, and having the relevant numbers... [and] we believe we have found that in the Gripen system.” The Gripen E will introduce “high tech, state-of-the-art systems,” he added. But “being a small country, we always have to think about money and affordability.” https://www.skiesmag.com/news/saab-delivers-virtual-gripen-e-program-update

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  29 mars 2019 | International, C4ISR, Sécurité, Autre défense

  DARPA Seeks to Make Scalable On-Chip Security Pervasive

  For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25