23 janvier 2020 | International, Aérospatial
The U.S. Air Force soon could deploy a radar-evading target drone. One that easily could evolve into a front-line warplane.
California-based Sierra Technical revealed its prototype drone in photos the company released in mid-January 2020.
The Fifth-Generation Aerial Target, or 5GAT, is roughly the size of a T-38 training jet and like the T-38 boasts two J85 engines. The prototype with its sharp angles bears a passing resemblance to an F-22 stealth fighter, albeit one without a cockpit.
The company plans to fly the drone for the first time in early 2020. The Air Force wants the 5GAT drone for target practice in order to help fighter pilots prepare for dogfights with Russian and Chinese stealth fighters.
The drone's development is part of a wider Air Force effort to provide realistic training to its pilots for doing battle with the latest radar-evading warplanes. The service also plans to organize some of its F-35 stealth fighters into an “adversary” squadron that would play the role of the enemy during realistic war games.
19 avril 2021 | International, Aérospatial
The Defense Advanced Research Projects Agency awarded three contracts this week to design a nuclear thermal propulsion system that will operate above low Earth orbit in 2025.
28 février 2024 | International, Aérospatial
7 novembre 2018 | International, C4ISR
DARPA program seeks to unleash the performance of modern multi-chip modules by integrating optical signaling at the chip-level OUTREACH@DARPA.MIL 11/1/2018 Parallelism – or the act of several processors simultaneously executing on an application or computation – has been increasingly embraced by the microelectronics industry as a way of sustaining demand for increased system performance. Today, parallel computing architectures have become pervasive across all application domains and system scales – from multicore processing units in consumer devices to high-performance computing in DoD systems. However, the performance gains from parallelism are increasingly constrained not by the computational limits of individual nodes, but rather by the movement of data between them. When residing on modern multi-chip modules (MCMs), these nodes rely on electrical links for short-reach connectivity, but once systems scale to the circuit board level and beyond, the performance of electrical links rapidly degrades, requiring large amounts of energy to move data between integrated circuits. Expanding the use of optical rather than electrical components for data transfer could help significantly reduce energy consumption while increasing data capacity, enabling the advancement of massive parallelism. “Today, microelectronic systems are severely constrained by the high cost of data movement, whether measured in terms of energy, footprint, or latency,” said Dr. Gordon Keeler, program manager in DARPA's Microsystems Technology Office (MTO). “Efficient photonic signaling offers a path to disruptive system scalability because it eliminates the need to keep data local, and it promises to impact data-intensive applications, including machine learning, large scale emulation, and advanced sensors.” Photonic transceiver modules already enable optical signaling over long distances with high bandwidth and minimal loss using optical fiber. Bottlenecks result, however, when data moves between optical transceivers and advanced integrated circuits in the electrical domain, which significantly limits performance. Integrating photonic solutions into the microelectronics package would remove this limitation and enable new levels of parallel computing. A new DARPA program, the Photonics in the Package for Extreme Scalability (PIPES) program, seeks to enable future system scalability by developing high-bandwidth optical signaling technologies for digital microelectronics. Working across three technical areas, PIPES aims to develop and embed integrated optical transceiver capabilities into cutting-edge MCMs and create advanced optical packaging and switching technologies to address the data movement demands of highly parallel systems. The efficient, high-bandwidth, package-level photonic signaling developed through PIPES will be important to a number of emerging applications for both the commercial and defense sectors. The first technical area of the PIPES program is focused on the development of high-performance optical input/output (I/O) technologies packaged with advanced integrated circuits (ICs), including field programmable gate arrays (FPGAs), graphics processing units (GPUs), and application-specific integrated circuits (ASICs). Beyond technology development, the program seeks to facilitate a domestic ecosystem to support wider deployment of resulting technologies and broaden their impact. Projections of historic scaling trends predict the need for enormous improvements in bandwidth density and energy consumption to accommodate future microelectronics I/O. To help address this challenge, the second technical area will investigate novel component technologies and advanced link concepts for disruptive approaches to highly scalable, in-package optical I/O for unprecedented throughput. The successful development of package-level photonic I/O from PIPES' first two technical areas will create new challenges for systems architects. The development of massively interconnected networks with distributed parallelism will create hundreds to thousands of nodes that will be exceedingly difficult to manage. To help address this complexity, the third technical area of the PIPES program will focus on the creation of low-loss optical packaging approaches to enable high channel density and port counts, as well as reconfigurable, low-power optical switching technologies. A full description of the program is available in the Broad Agency Announcement. For more information, please visit: https://www.fbo.gov/spg/ODA/DARPA/CMO/HR001119S0004/listing.html https://www.darpa.mil/news-events/2018-11-01