23 novembre 2024 | International, Aérospatial

Romania Becomes the 20th Member of the F-35 Global Alliance

This decision marks a significant milestone in Romania's defense strategy and its commitment to maintaining a robust and advanced military force.

https://www.epicos.com/article/891509/romania-becomes-20th-member-f-35-global-alliance

Sur le même sujet

  • Les députés allemands adoptent le fonds spécial de 100 Md€ pour la Bundeswehr

    10 juin 2022 | International, Terrestre

    Les députés allemands adoptent le fonds spécial de 100 Md€ pour la Bundeswehr

    Les députés allemands ont adopté, vendredi, à une très large majorité, la dotation de 100 Md€ proposée en février par le chancelier Olaf Scholz à destination de la modernisation de son armée. Cette dotation exceptionnelle a été votée non seulement par les partis de sa coalition (SPD, Grünen, et FDP), mais aussi par le groupe conservateur (CDU-CSU), principale force d'opposition au Bundestag, dont le chancelier avait besoin du soutien pour garantir que ce fonds spécial soit inscrit dans la Loi fondamentale allemande. C'est l'Armée de l'Air qui bénéficiera de la plus grosse part du fonds : 33,4 Md€ serviront notamment à payer les 35 avions de combat F-35 que le gouvernement allemand a décidé d'acheter au constructeur américain Lockheed Martin. Berlin entend également acquérir des avions de chasse Eurofighter ECR, fabriqués par le consortium européen Airbus, des hélicoptères de transport Chinook CH-47-F, produits par l'américain Boeing, ainsi que des drones Heron TP, de fabrication israélienne. « Le développement du Système aérien de combat du futur (SCAF) doit lui aussi être financé par le fonds spécial à partir de 2023 », a par ailleurs déclaré la ministre allemande de la Défense, Christine Lambrecht, en référence au projet germano-franco-espagnol censé aboutir en 2040. L'Armée de Terre et la Marine sont dotées de 16,6 et de 8,8 Md€ respectivement. L'argent débloqué doit également être mis au service d'un projet européen : le char de combat du futur (MGCS). Quant au reste de l'enveloppe, il ira à des programmes transversaux. Environ 20 Md€ seront par exemple affectés à la numérisation de la Bundeswehr, terme qui recouvre aussi bien l'acquisition de nouveaux matériels de communication que le financement de systèmes satellites. Le Monde et Financial Times du 6 juin

  • DARPA Seeks to Make Scalable On-Chip Security Pervasive

    29 mars 2019 | International, C4ISR, Sécurité, Autre défense

    DARPA Seeks to Make Scalable On-Chip Security Pervasive

    For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25

  • Berlin plans to spend 8 billion euros in package for 60 Boeing Chinook helicopters

    23 juin 2023 | International, Aérospatial

    Berlin plans to spend 8 billion euros in package for 60 Boeing Chinook helicopters

    Germany aims to purchase 60 Chinook helicopters from Boeing in a package that would cost up to 8 billion euros ($8.71 billion), including necessary infrastructure for the aircraft, a parliamentary source told Reuters on Friday.

Toutes les nouvelles