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  16 juillet 2019 | International, Aérospatial, Autre défense

  New Army cyber gear for drones and teams test, protect units in another domain

  By: Todd South A prototype device used recently at the Army's premiere combat training center has soldiers using precision cyber techniques to target small drones that might have been missed with other equipment and methods. Soldiers with the 3rd Brigade Combat Team, 1st Cavalry Division used the cyber precision drone detection system during a January rotation at the National Training Center. The equipment allowed soldiers to get alerts of drone presence and ways to target it that helped protect the brigade, according to an Army release. Capt. Christopher Packard said the prototype integrated with existing signal, intelligence and electronic warfare capabilities. Five soldiers embedded with the opposing force to attack the brigade with enemy drones for more realistic training, according to the release. A group of software developers at the Army's Cyber Command along with others at the Defense Digital Service built custom software and modified commercial equipment to make the early versions of the prototype last year. “The (Rapid Capabilities and Critical Technologies Office) and Tobyhanna (Army Depot) helped out with taking it from an advanced prototype and turning it into an engineering design model,” said 1st Lt. Aneesh Patel, with ARCYBER's Cyber Solutions Development Detachment with the 782nd Military Intelligence Battalion, 780th Military Intelligence Brigade. “We designed our own hardware and schematics, but what we didn't have was the proper ability to scale, and I think that's important in a bridging strategy and for any prototype.” The system is an “interim solution,” according to the release. “Being a newer system and a new tool for a maneuver unit, there are going to be a lot of things we don't know as [cyber] engineers, and a lot of their specific needs for the capability that may not have gotten through to us. So being out there was very important to this and any other project like it,” Patel said. The system will be followed by an upgraded version slated for Special Operations Command for an operational assessment this summer. Phase two will maximize the capability's operational life span by adding software updates that improve performance, according to the release. That type of equipment hits drones, but the Army also has its own cyber protection teams, such as the one featured in another release out of Grafenwoehr, Germany in June, where the 301st and 172nd CPTs used defensive measures for the Sabre Guardian 19 exercise. The annual exercise is taking place this year in Bulgaria, Hungary and Romania, co-led by the Romanian Joint Force Command. The teams “create chaos by accessing the network and either disabling it or stealing classified information and using it against the units involved in the exercise.” Though cyber threats have been a talking point among commanders for years, it wasn't until this most recent rotation that cyber threats were simulated for the exercise, said Capt. Joe McNerney, 301st CPT battle captain. The captain explained that the CPTs simulate an insider threat. The 172nd is a combination of soldiers and airmen from units based in Indiana, Michigan and Ohio. The 301st is an Air Force unit out of the Battle Creek Air National Guard Base, Michigan. “They're people we work with on a daily basis so we want to beat them," said Sgt. Brian Stevens, an information technology specialist from Detroit. “We have to make them feel pain at some level.” https://www.armytimes.com/news/your-army/2019/07/15/new-army-cyber-gear-for-drones-and-teams-test-protect-units-in-another-domain/

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  20 juin 2018 | International, Naval

  GenDyn contracted for parts for future submarine construction

  James LaPorta June 19 (UPI) -- The Department of Defense has awarded a contract to General Dynamics Electric Boat for work on the next nine Virginia-class attack submarines. The contract award from Naval Sea Systems Command, announced Monday, is worth $225 million under the terms of cost-plus-fixed-fee contract, which is a modification to a previous Pentagon award, the Defense Department said. The deal will see General Dynamics provide economic ordering quantity material -- parts ordered ahead of time -- for the next nine Virginia-class, nuclear-powered fast attack submarines, for work in fiscal 2019 through 2023. The nine vessels are part of the Block V generation of the Virginia class. The first four have been ordered by the U.S. Navy already, with General Dynamics set to construct SSN-802 and SSN-803 and Huntington Ingalls Industries tapped for SSN-804 and SSN-805. Work on the contract will occur in various locations throughout the United States and is expected to be complete in January 2019. The total cumulative value of the contract will be obligated to General Dynamics at time of award -- the obligated funds will be allocated from Navy fiscal 2018 shipbuilding and conversion accounts and will not expire at the end of the current fiscal year, said the Pentagon press release. https://www.upi.com/Defense-News/2018/06/19/GenDyn-contracted-for-parts-for-future-submarine-construction/8941529412778/

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  29 mars 2019 | International, C4ISR, Sécurité, Autre défense

  DARPA Seeks to Make Scalable On-Chip Security Pervasive

  For the past decade, cybersecurity threats have moved from high in the software stack to progressively lower levels of the computational hierarchy, working their way towards the underlying hardware. The rise of the Internet of Things (IoT) has driven the creation of a rapidly growing number of accessible devices and a multitude of complex chip designs needed to enable them. With this rapid growth comes increased opportunity for economic and nation-state adversaries alike to shift their attention to chips that enable complex capabilities across commercial and defense applications. The consequences of a hardware cyberattack are significant as a compromise could potentially impact not millions, but billions of devices. Despite growing recognition of the issue, there are no common tools, methods, or solutions for chip-level security currently in wide use. This is largely driven by the economic hurdles and technical trade-offs often associated with secure chip design. Incorporating security into chips is a manual, expensive, and cumbersome task that requires significant time and a level of expertise that is not readily available in most chip and system companies. The inclusion of security also often requires certain trade-offs with the typical design objectives, such as size, performance, and power dissipation. Further, modern chip design methods are unforgiving – once a chip is designed, adding security after the fact or making changes to address newly discovered threats is nearly impossible. “Today, it can take six to nine months to design a modern chip, and twice as long if you want to make that same design secure,” said Serge Leef, a program manager in DARPA's Microsystems Technology Office (MTO). “While large merchant semiconductor companies are investing in in-house personnel to manually incorporate security into their high-volume silicon, mid-size chip companies, system houses, and start-ups with small design teams who create lower volume chips lack the resources and economic drivers to support the necessary investment in scalable security mechanisms, leaving a majority of today's chips largely unprotected.” To ease the burden of developing secure chips, DARPA developed the Automatic Implementation of Secure Silicon (AISS) program. AISS aims to automate the process of incorporating scalable defense mechanisms into chip designs, while allowing designers to explore economics versus security trade-offs and maximize design productivity. The objective of the program is to develop a design tool and IP ecosystem – which includes tool vendors, chip developers, IP licensers, and the open source community – that will allow security to be inexpensively incorporated into chip designs with minimal effort and expertise, ultimately making scalable on-chip security pervasive. Leef continued, “The security, design, and economic objectives of a chip can vary based on its intended application. As an example, a chip design with extreme security requirements may have to accept certain tradeoffs. Achieving the required security level may cause the chip to become larger, consume more power, or deliver slower performance. Depending on the application, some or all of these tradeoffs may be acceptable, but with today's manual processes it's hard to determine where tradeoffs can be made.” AISS seeks to create a novel, automated chip design flow that will allow the security mechanisms to scale consistently with the goals of the design. The design flow will provide a means of rapidly evaluating architectural alternatives that best address the required design and security metrics, as well as varying cost models to optimize the economics versus security tradeoff. The target AISS system – or system on chip (SoC) – will be automatically generated, integrated, and optimized to meet the objectives of the application and security intent. These systems will consist of two partitions – an application specific processor partition and a security partition implementing the on-chip security features. This approach is novel in that most systems today do not include a security partition due to its design complexity and cost of integration. By bringing greater automation to the chip design process, the burden of security inclusion can be profoundly decreased. While the threat landscape is ever evolving and expansive, AISS seeks to address four specific attack surfaces that are most relevant to digital ASICs and SoCs. These include side channel attacks, reverse engineering attacks, supply chain attacks, and malicious hardware attacks. “Strategies for resisting threats vary widely in cost, complexity, and invasiveness. As such, AISS will help designers assess which defense mechanisms are most appropriate based on the potential attack surface and the likelihood of a compromise,” said Leef. In addition to incorporating scalable defense mechanisms, AISS seeks to ensure that the IP blocks that make up the chip remain secure throughout the design process and are not compromised as they move through the ecosystem. As such, the program will also aim to move forward provenance and integrity validation techniques for preexisting design components by advancing current methods or inventing novel technical approaches. These techniques may include IP watermarking and threat detection to help validate the chip's integrity and IP provenance throughout its lifetime. AISS is part of the second phase of DARPA's Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. Under ERI Phase II, DARPA is exploring the development of trusted electronics components, including the advancement of electronics that can enforce security and privacy protections. AISS will help address this mission through its efforts to enable scalable on-chip security. DARPA will hold a Proposers Day on April 10, 2019 at the DARPA Conference Center, located at 675 North Randolph Street, Arlington, Virginia 22203, to provide more information about AISS and answer questions from potential proposers. For details about the event, including registration requirements, please visit: https://www.fbo.gov/index?s=opportunity&mode=form&id=6770487d820ee13f33af67b0980a7d73&tab=core&_cview=0 Additional information will be available in the forthcoming Broad Agency Announcement, which will be posted to www.fbo.gov. https://www.darpa.mil/news-events/2019-03-25